The names of the input signals of type type. type can be any of BOOL, INT and REAL.
If this key is found in a line of the template file during code generation, then that whole line will be copied the same number of times as there are input signals of type type, and in each copy, the %type_INPUT_NAMES% key is replaced by the name of an input signal.
An input signal in the code generation context is an input signal of the top-level node. Inputs of subnodes count as local signals.
VHDL
entity RTflowCode is port( %BOOL_INPUT_NAMES% : in std_logic; %INT_INPUT_NAMES% : in integer; %REAL_INPUT_NAMES% : in float32; %BOOL_OUTPUT_NAMES% : out std_logic; %INT_OUTPUT_NAMES% : out integer; %REAL_OUTPUT_NAMES% : out float32; clk : in std_logic ); end RTflowCode;