Code Generator - General

RTflow can generate implementation code from the model, so that it can be implemented in a real-world application. To be more precise, RTflow can generate C, C++ and Java for software implementations and synthesizable VHDL for FPGA/ASIC implementations. Code generation is performed by invoking the Generate Code command. The first time, you will be asked to set up some code generation settings in the project settings dialog. Subsequent invocations require no further user interaction.

Template files

Among a few other settings for code generation, you have to specify a template file. The template file defines the interface of the generated file by means of skeleton functions that contain code generation keys. The code generator reads the template file and outputs a copy of it, but with the keys replaced by actual generated code. Most users don't need to write their own template file, but can use the ones supplied with RTflow - see the table below. However, advanced users may prefer to write their own template file. The Key Reference provides the primary documentation for those users.

The template files supplied with RTflow are (paths are relative to the application folder):

Target Language Path
C Templates/Template.c
C++ Templates/Template.cpp
Java Templates/Template.java
VHDL Templates/Template.vhd

It is recommended to copy the template file to the project folder, to ensure that the project can be moved to other computers.