%type_VECTOR%

The name of the type array. type can be any of BOOL, INT and REAL, such that the actual keys are %BOOL_VECTOR%, %INT_VECTOR% and %REAL_VECTOR%.

Rather than declaring one single variable (in VHDL: signal) for each signal of the RTflow model, the code generator expects the existence of arrays (in VHDL: vectors), in which all signals reside. Hence, the generated code is merely a sequence of computations on elements of these arrays. There must be one array for each of the basic types boolean, integer and real, and it is the template author's responsibility to declare these appropriately. To do this, the array names that are used in the generated code must be known, and these are given by the %type_VECTOR% key.

Generators

C/C++/Java, VHDL

Example (Java)

%IF_HAS_REAL%   public float[] %REAL_VECTOR% = new float[%NUMBER_REAL%];

Example (VHDL)

%IF_HAS_BOOL%   signal %BOOL_VECTOR% : std_logic_vector(%NUMBER_BOOL%-1 downto 0);