Key Reference

The following table summarizes the code generation keys that will be recognized in the template file. type can be any of BOOL, INT and REAL. Keys are case sensitive and are always in capital letters. Most of the keys can be used with both the C/C++/Java generator and the VHDL, while a few keys are unique for one of the generators. The table specifies with an X for which code generators the key can be used.

Key Description C/C++/Java VHDL
%type_VECTOR% The name of the type array. X X
%IF_HAS_type% Includes the line if and only if there are type signals. X X
%type_NAMES% The names of the signals and states in the type array. X
%type_INPUT_NAMES% The names of the input signals of type type. X
%type_OUTPUT_NAMES% The names of the output signals of type type. X
%NUMBER_type% The total number of type signals. X X
%NUMBER_type_INPUT% The number of type input signals. X X
%NUMBER_type_OUTPUT% The number of type output signals. X X
%NUMBER_type_LOCAL% The number of type local signals. X X
%NUMBER_type_STATE% The number of type state variables. X X
%OFFSET_type_INPUT% The index of the first input signal in the type array. X X
%OFFSET_type_OUTPUT% The index of the first output signal in the type array. X X
%OFFSET_type_LOCAL% The index of the first local signal in the type array. X X
%OFFSET_type_STATE% The index of the first state variable in the type array. X X
%INITIAL_EQUATIONS% Code that resets all state variables to the initial state. X X
%OUTPUT_UPDATE_EQUATIONS% Code that computes all local and output signals from the current inputs and states. X X
%STATE_UPDATE_EQUATIONS% Code that transitions the state variables to the next cycle. X X
%SAMPLE_TIME% The real time in seconds corresponding to one execution cycle. X
%FREQUENCY_MHZ% The frequency in MHz of the clock that will drive the implementation. X
%INPUT_MAP% Code that copies input signals from the entity's interface to the arrays. X
%OUTPUT_MAP% Code that copies output signals from the arrays to the entity's interface. X